Binary coded decimal counter circuits



Aug. 2, 1966 A. PRIETO 3,264,567

BINARY GODED DECIMAL COUNTER CIRCUITS jli IT'Ii Z4 j l /rf' 1 l INVENTOR. Q57. Z Za f Z" iwf/envy @f7/fra -Y.-J 52u46 @vom Aug. 2, 1966 A. PRlETo 3,264,567

BINARY CCDED DECIMAL COUNTER CIRCUITS Filed July 2, 1964 4 Sheets-Sheet 2 IN VEN TOR. /631/ ffm/y 0f/70 ifraf/rfy A. PRIETO BINARY CODED DECIMAL COUNTER CIRCUITS Aug. 2, l1966 4 Sheets-Sheet 3 Filed July 2, 1964 Aug. 2, 1966 A. PRIETO 3,264,567

BINARY CODED DECIMAL COUNTER CIRCUITS Filed July 2, 1964 4 Sheets-Sheet 4 ifm/wey United States Patent 3,264,567 BINARY CODED DECIMAL COUNTER CIRCUITS Anthony Prieto, Palm Beach Gardens, Fla., assignor to Radio Corporation of America, a corporation of Delaware Filed `Iuly 2, 1964, Ser. No. 379,815 4 Claims. (Cl. 328-45) This invention relates to improved binary coded decimal counters.

A binary coded decimal counter includes successive stages, each with four storage elements. In the case of an up counter, for example, each stage counts to 9 and, in response to the tenth input pulse, resets to 0 and generates a carry to the succeeding stage. In some prior art counters, the various stages each include a group of auxiliary flip-flops which temporarily store the ninth count. In response to the tenth count, these Hip-flops generate a reset signal for the stage and a carry signal for the following stage. Known binary coded deci-mal down counters employ similar circuits for temporary storage and generation of the reset and borrow signals.

An object of the present invention is to provide a circuit which is simpler than the one discussed above and which operates at relatively high speed.

In the circuit of the present invention, the auxiliary hip-flops in each stage for temporarily storing the ninth count are not employed. In the present circuit, there are logic gates connected to each two-state storage device through some of which the pulses to be counted are applied to the two-state device. These logic gates themselves sense the count produced by the counter and, when it reaches a predetermined value, automatically reset the counter and generate the carry (or borrow) for the following stage. The teachings of the invention are applicable both to up counters and to down counters.

The invention is discussed in greater detail below and is shown in the following drawings, of which:

FIGURES la-lg show the symbols employed for the logic circuits, such as gates, in the following figures and include also the Boolean equations and truth tables which describe the manner in which the circuits operate;

FIGURE 2 is a block circuit diagram of one form of binary coded decimal up counter;

FIGURE 3 is a block circuit diagram of another embodiment of an up counter a-ccording to the invention;

FIGURE 4 is a block circuit diagram of a second counter stage according to the invention;

FIGURE 5 is a drawing of waveforms to help explain the operation of the circuit of FIGURE 4;

FIGURE 6 is a block circuit diagram of three stages of a binary coded decimal counter according to the invention;

FIGURE 7 is a block circuit diagram of a binary coded decimal down counter according to the invention; and

FIGURE 8 is a block circuit diagram of the second (102) stage of the binary coded decimal down counter.

Throughout the drawings, similar reference numerals are applied to similar circuit elements. Also, the numerals 1, 2 and 3 are used to designate the iirst, second and third inputs to the different gates to keep the charts simple.

In the circuits to be discussed, electrical signals represent binary digits, hereafter termed bits The convention is arbitrarily adopted that a low level signal represents the bit l and a high level signal represents the bit 0. For the sake of simplifying the discussion which follows, the bit itself is referred to rather than the signal manifesting the bit.

The symbols of FIGURES la-lg are fairly standard. The truth tables and Boolean expressions dene the operation of the various circuits. With respect to the triggerable Hip-liop, in the remaining figures, the set (S) 3,264,567 Patented August 2, 1966 terminal and the clear (C) terminal are not shown. However, it is to be understood that they are present and that any flip-tiop can be made to store a l by applying a 1 to the set terminal and a 0 to the clear terminal, and can be made to store a 0 by applying a l to the clear terminal and a 0 to the set terminal. Storage of a 1 in the ip-flop is indicated by a l present at the 1 output terminal and a 0 present at the 0 output terminal. Stor age of a 0 in the llip-flop is indicated by a 0 present at the l output terminal and a l present at the 0 output terminal.

The first stage of a binary coded decimal up counter is shown in FIGURE 2. It includes NAND gates 10, 12 and 14. NAND gate 10 applies its output U through inverter ,22 to the trigger terminal T of the ip-flop 26. NAND gate 12 applies its output E through inverter 20 to the trigger terminal of the flip-Hop 28. The output of NAND gate 14 serves as one input to NAND gates 16 and 18. The other input to NAND gate 16 is the output of NAND gate 12. The other input to NAND gate 18 is from the 0 output terminal of ilip-tiop 23. AND gate 32 receives the outputs of NAND gates 16 and 18 and applies its output to the trigger terminal of the flip-flop 30.

The operation of the circuit of FIGURE 2 succinctly is given in the following table. The following explanation of a number of the steps shown in Table l will help the reader to interpret the table.

Initially, a count is inserted in the four stages shown by applying appropriate signals to the set and reset terminals (not shown) of the hip-flops. However, for purposes of the present explanation, it may be assumed that the initial count is 0000 which is indicative of the deci mal number 0. The conditions which then exist are those shown in the last line of the table.

The leading edge of the first P0 timing pulse legended TP-l in FIGURE 2 changes the state of flip-ilop 24. This leading edge denes a l-to0 transition and, as is seen from FIGURE lg, it is this transition that causes a change in the state of a flip-flop. The three inputs 1, 2, 3 of NAND gate 10 are then switched to l, l, 0 so that 1-1. The three inputs 1, 2, 3, of NAND gate 12 are 0, l, 0 so that Fzl. The two inputs -to NAND gate 14 are 0, l causing this NAND gate to produce a 1 output. The inputs to NAND gates 16 and 18 both are l, l so that both NAND gates produce 0 outputs and A, the output of AND gate 32, is 0.

In response to the trailing edge of TP-l, that is, the 0-to1 transition, the three inputs to NAND gate 10 become l, l, l. therefore switches from l to 0 and C switches fom 0 to l. The 0-to-l transition of C does not change the state of flip-flop 26, but places it in condition to change states.

The leading edge of the next timing pulse TP-2 changes the state of flip-Hop 24 so that its output becomes 0. The three inputs to NAND gate 10 are now l, 0, 0 so that U changes from 0 to l and C changes from l to 0. The l-to-O transition of C triggers ip-op 26 changing its output from 0 to 1. Accordingly, the second timing pulse TP-Z changes the count from 0001 to 0010.

Skipping now to timing pulse 8, upon termination ol lthis timing pulse, the count recorded in the counter is 1000. The leading edge of timing pulse TP-9 changes the count to 1001, the binary equivalent of the decimal numeral 9. This ninth pulse also causes A, the input to the last flip-flop 30, to change from 0 to l, conditioning ip-op 30 to be switched.

The ninth timing pulse also changes the inputs ot NAND gate 14 from 0, l to l, l thereby causing its output P1 to change from l to 0. This l-t-o-0 Itransit-ion is applied to the following stage through an inverter. Ac-

cordingly, the following stage receives a O-to-l transition which does not change the state of the next stage.

The tenth timing pulse TP-lO switches the state of flipop 24 from 1 to 0. This causes P1 to change from 0 to 1, causing the'following stage to receive a 1-tfo-0 change at the output of inverter 40 of FIGURE 4. (This 1-to-0 transition may be considered the carry.) Itralso causes A to change from 1 to 0 triggering ip-iiop 30, causing 4i it to switch back to theO'state.

Summarizingthe operation above, the counter shown in FIGURE 2 'counts the rst nine input pulses it receives and produces on its four Youtput=leads legended 23, 22, 21and 20 a binary coded` decimaloutput. The tenth timing pulse automatically resets the ipE-ops to their 0 state and causes a carry P to begenerated.' Thisv carry is applied Vto the following stage.y

TABLE I 1-0=1 to 0 transition. 0-1=0 1 transition.

Gate 14 Gate l16 Gate 18 OOOQOOOOGOQOOO a OOoOcoDTv-*-Hr-Hl-l i. O

cPOoOoOOOOOQo H.

TP-S

TP-lO *Gate 16 input changes before gate 18 input changes. Therefore, the output of gate lchanges to 0 before the output of gate 18 changes toY 1.

TABLE 2 ocaccooooopbo 5 The circuit of FIGURE 2 employs NAND gates and inverters as these are standard components which were readily available during the circuit design. An example of another circuit embodying the invention appears in the count thereupon advances to 0001. Each subsequent tenth timing pulse P0 causes the count stored in the second stage of the counter also to advance by one.

FIGURE 6 shows three stages of the counter accord- FIGURE 3. The latter Circuit employs four AND gat-SS 5 ing to the invention. The first and second stages have 90, 92, 94 and 104 and one OR gate U12-a total `of only already been discussed. The third or 102 stage is exfive gates rather than the five NAND gates, two inverters actly the same as the 101 stage. However, a NOR gate and One AND gate-a total 0f eight logical elements 0f 52 is substituted for inverter 40. This NOR gate re- FIGURE 2- lIl ddOIL the CICU 0f FIGURE 3 has ceives the carry toutputs P1 and P2 of the first and second the advantage that the carry which is generated is F1 10 stages, respectively. Each time both of these carries rather than P1 so Ithat inversion is not required between become equal to 0, the NOR gate 52 produces a l output. the iirst and second stages of the counter. v Thereafter, when one of the inputs P1 or P2 changes back The operation of the circuit of FIGURE 3 is given in to 1, the NOR gate produces a 1-to0 transition which Table Ziabove. conditions the gates of the third stage to be triggered The circuit of FIGURE 4 is the second (101) stage 15 by the Po trigger pulses. of the binary coded decimal counter, the first stage of FIGURE 7 illustrates the first stage of a count-down which is shown in FIGURE 2. The circuit of FIGURE binary coded decimal counter. It includes three NAND 4 includes allof the components of FIGURE 2 and also gates 61, 62 and 63 and three inverters 65, 66 and 67. includes a NAND gate 42 and inverter 44. The inverter The circui-t also includes four iipdiops 68, 69, 70 and 71 44 applies its output D to the trigger terminal of the irst 20 and a NAND gate 64 connected to the 0 output terminals dip-dop 24a. In addition, there is an inverter 40 which of the flip-flops. NAND gate 64 produc-es the borrow receives the carry output P1 and supplies the inverted carry output P1 which is applied t-o the following stage and is F1 to the NAND gates 42, 10a and 12a. also employed to reset the counter to its original condi- The operation of the circuit of FIGURE 4 is analogous tion. The operation -of the counter of FIGURE 7 is set to that of the circuit of FIGURE l. As shown in FIG- 25 forth in the following Table 3. `If the assumption marde URE 5, when the ninth timing pulse occurs, Po changes is that the count initially stored is 0000, as set forth in from 1 to 0 and P1 changes from 1 to Q the Output the first line of the table, the first input pulse changes the of NAND gate 42, is therefore l and D is 0. In response count to 1001, the binary coded equivalent of 9, and to the O-to-l transition ofthe trailing edge of timing pulse bOrrOWS from the tenth stage. Each succeeding pulse TP-9, the inputs to NAND gate 42 change to l, 1. This 30 reduces the count by one, until the ninth pulse is reached. causes to Switch from 1 to 0 and D to Switch from The ninth pulse causes the count 0001 to be produced. 0 to l. The D=1 applied to the trigger terminal of iiip- The tenth pulse resets the Count to 0000 and produces iop 24a conditions the flip-flop to change its state. a borrow condition which will allow any .additional trigthe count initially in the 10 stage of the counter is 0000, ger pulse to borrow from the tenth stage.

TABLE 3 Pulse No.

OQOOOOO When the leading edge of the next timing pulse TP-lO occurs, the inputs to NAND gate 42 change to 0, 0 so that D changes from 1 back to 0. This 1-to-0 transition QOOOOOOO i The second stage of the count-down counter is shown in FIGURE 8. It includes, in addition to the circuit elements of FIGURE 7, an additional NOR gate 73 and triggers flip-flop 24a, causing it to change its state. If 75 inverter 75. The output of the inverter goes to the trigger `terminal of the firstflip-op 68..` The borrow input P1` is applied through an inverter `77 to the NAND w gates 63a, 62a, 61a yand 73. The borrow output Pz'of the second stage is applied to a NOR gate 79. The sec ond input'to the NOR gate is the borrow P1 generated by the first` or 10 stage.v The NOR gate79 at the input to the 'third stage performs a function analogous to that of the inve-rter 77 located yat the input to the secondfstage, The output of NOR gate 79 is applied to, the NAND gates corresponding to 63a, 62a, 61a and 73 of the third or 102 stage;

While not illustrated, it is to be understood that other embodiments arepossible of the binary..coded decimal` countfdown counter of FIGURES 7 and 8. fFor example, AND and OR gates may be employed rather than NAND gates yand inverters, in a manne-r similar to that v shownfor the up counter.

of FIGURES 4 and 6 may be designed in accordance with the teachings of FIGURE 3.

In the claims which follow, the term carry is emf;

ployed in the generic sense to yrefer to the output` of -a By the ksarne token, .the sec` ond, third .andhigher order stagesof the count-up coun-ter counter stage, either count-down or count-up,iwhich ist` employed to trigger the following counter stage.

What is claimed is:

1. A'stage of `a binary coded decimal counter con1.

prising, in combination:`

four `two-state ydevices forstoring the 20, ,21,` 22` and 231 bits, respectively,.of a binary codeddecimal number; rst, second and third logic circuits, connected to the 21, 22" and 23 two-state devices, respectively, fory applying triggeringsignals to said devices, and said third logic circuits for also producing a carry signal;

means for applying the pulses to be counted to the 20 two-state device, and -the rst and second logic circuits;

means Vfor applyingan output of the 2 vtwo-state device to all three logic circuits;

means for applying Ian output of the 21 two-state device to the second logic circuit;

means-for applying an output of the 22 two-state device to the third logic circuit;

means. for applying one output ofthe 23 two-state Si@l devicerto the third logic circuit andthe complement ofsaid output to the first logic circuit; and- A means ,for applying .an output` from the, secondlogicv circuit to the third logic circuit.y

2. A stage as set forth in claim 1 .wherein all of said logic circuits include .at least one NANDA gate.

3. `A stage as: set forth in lcl-airn'Z whereinzsaidthird logic circuitcomprises three NAND gates. andan AND gate.y

4. A stage rof 'abinary coded decimal; counter acomprising, in combination:

four two-state devicesnfor storing: the 20,521, 22 and 23.

bits, lrespectively lof a Ybinary. coded decimal number; rst, second, third and.four.thilogic circuits, connected to the 2, 21, -22 and 2? two-state devices, respectively,

for applying triggering .signals to said devioes,and. said fourth logic. circuit for also producing `a carryf ing signal; l

means for applyinggthe pulses to be= counted to the first, second and {third logic circuits;

means forapplying an output of fthe 2.`tWo-state device r to the second, third-and fourth 'logicfcircuits means for applying an output ofthe 21;.two-state device...`

to the thirdtlogici circuit; f

means for applying .an output ofthe 22. two-sta-te device to the fourth `logic circuit; means for applying .onexoutputl of the 23' two-state device tothe fourth logic.. circuit andthe ,comple-- lment of said, loutput to the; second logic circuityand meansV for applying an ,output from the'rthird ylogic 6/1959 Crosby soif- 88.5.- 5/-1965 vLauer; t 307-885 

1. A STAGE OF A BINARY CODED DECIMAL COUNTER COMPRISING, IN COMBINATION: FOUR TWO-STATE DEVICES FOR STORING THE 20, 21, 22 AND 23 BITS, RESPECTIVELY, OF A BINARY CODED DECIMAL NUMBER; FIRST, SECOND AND THIRD LOGIC CIRCUITS, CONNECTED TO THE 21, 22 AND 23 TWO-STATE DEVICES, RESPECTIVELY, FOR APPLYING TRIGGERING SIGNALS TO SAID DEVICES, AND SAID THIRD LOGIC CIRCUITS FOR ALSO PRODUCING A CARRY SIGNAL; MEANS FOR APPLYING THE PULSES TO BE COUNTED TO THE 20 TWO-STATE DEVICE, AND THE FIRST AND SECOND LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 20 TWO-STATE DEVICE TO ALL THREE LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 21 TWO-STATE DEVICE TO THE SECOND LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 22 TWO-STATE DEVICE TO THE THIRD LOGIC CIRCUIT; MEANS FOR APPLYING ONE OUTPUT OF THE 23 TWO-STATE DEVICE TO THE THIRD LOGIC CIRCUIT AND THE COMPLEMENT OF SAID OUTPUT TO THE FIRST LOGIC CIRCUIT; AND MEANS FOR APPLYING AN OUTPUT FROM THE SECOND LOGIC CIRCUIT TO THE THIRD LOGIC CIRCUIT. 